cos/mos quad exclusive-or gate the rca-cd4030a types consist of four in- dependent exclusive-or gates integrated on a single monolithic silicon chip. each ex- clusive-or gate consists of four n-channel and four p-channel enhancement-type transistors. all inputs and outputs are protected against electrostatic effects. these types are supplied in 14-lead hermetic dual-in-line ceramic packages (0 and f suffixes), 14-lead dual-in-line plastic pack- age (esuffix), 14-lead ceramic flat package (k suffix), and in chip form (h suffix). maximum ratings, absolute maxlfilum values storage temperature range it,,q' operating temperature range ita' package types 0 f h package type e ocsupplyvoltage range iv oo ' 55 to + 125c 40 to +8soc (voltages referenced to vss terr""'dll 0 5 to +15 v power dissipation per package ipo' for tae 40to -6qoc (package type ei ~oomw for ta - -60 to -85c ipacka~e type e' derate linearly at 1'z mwloc to 'zoo mw for t a' 55 to ? 100c ipackage types 0 f i 500 mw for t a " + 100 to "25 0 c ipackage types 0 f i opr.iip l"w ?? rly.1i 17 rnw c to 700 mw for t a' full package temperature range (all package typesi 100 mw _ vice dissipation per output transistor put vol tage range. all inputs 05 to voo 0 s v lead temperature louring soldering' at d,stance 1/ 16 ! 1132 inch (1 59 ? 0 79 mrn' fr or" c.,,,, lor 10, m ... recommended operating conditions at ta = 25 0 c, for maximum reliability, nommal operatmg conditions should lje selected so that operation is always wlthm the followmg ranges' limits e d,f,h characteristic packages package units min. max. supply voltage range (for t a = full package temperature range) 3 12 ? 4ll inputs are protected by cds/mds protection network truth table foroneof four identical gates a b j 0 0 0 1 0 1 0 1 1 1 1 0 all p - channel substrates are internally connecteo to vod all n- channel substrates where "1" a high level are internally connected to vss "0" " low level min. max. 3 12 fig_' - schematic diagram (or' o( 4 identical exclusive-or gates. v for quietcllnt device current, noise immunity, end input lakege current test circuits ... "retinlllend cherecteriltics" et the beginning of the cos/mos liction. cd4030a typ s vss j'a0b l' e0f k'c0d m'g0h 14 vd d 13 h 12 g ii m 10 l 9 f b e functional diagram features: ? medium speed operation. .?. tphl = tplh = 40 ns (typ.) @ cl = 15 pf and vdd-vss = 10 v ? low output impedance. _ . ... 500 n (typ.) @ vdd-vss = 10 v ? quiescent current specified to 15 v ? maximum input leakage current of 1 j.l.a at 15 v (full package-temperature range) ? 1-v noise margin (full package-temper- ature range) applications: ? even and odd-parity generators and checkers ? logical comparators ? adderslsubtractors ? general logic functions daain-to-$ource volts lvos' flg.2 - typical output n-channel drain characteristics. drain-to-source vdltstvos' fig.3 - typical output p-channel dram characte"stics. 505
cd4030a typ s static electrical characteristics conditions limits at indicated temperatures (oc) characteristic d,f,h packages e package vo vin vdd -55 +25 +125 -40 +25 (v) (v) (v) typ. limit typ. limit quiescent device - - 5 05 0.005 05 30 5 0.05 5 current i l max - - 10 1 001 1 60 10 0.1 10 - - 15 25 05 25 1000 250 2.5 250 output voltage - 5 5 o typ., 0.05 max. low level, - 10 10 o typ ; 0.05 max. vol high level - 0 5 4.95 mm., 5 typ. voh - 0 10 995 mm .. 10 typ noise immunity inputs lolli(. 3.6 - 5 1.5 mm., 2.25 typ. vnl 72 - 10 3 mm, 4.5 typ inputs high 14 - 5 1.5 min, 2 25 typ vnh 2.8 - 10 3 min ,4 5 typ. noise margin: inputs low, 45 - 5 1 min. vnml 9 - 10 1 min. inputs high, 0.5 - 5 1 min. vnmh 1 - 10 1 min. output drive current n channel (sink) 05 - 5 0.75 1.2 06 045 035 1.2 03 ion min. 0.5 - 10 1.5 24 1.2 0.9 0.7 2.4 06 pchannel (source). 45 - 5 -0.45 -06 -0.3 -021 -0.21 -0.6 -0.15 idp min. 9.5 - 10 -095 -13 -0.65 -045 -0.45 -1.3 -032 input leakage any input current -\ - \15 iil,iih 10- 5 typ., 1 max. dynamic electrical characteristics at t a = 25 0 c, input t r , tt = 20 ns, cl = 15 pf, rl = 200 kn limits characteristic test conditions d,f,h e rvoo packages package (v) min. typ. max. min. typ. max. propagation delay 5 - 100 200 - 100 300 time: 10 40 100 40 150 tplh, tphl - - transition time. hlghtolow 5 - 70 150 - 70 300 10 - 25 75 - 25 150 level, tthl lowtoh igh 5 - 80 150 - 80 300 level, ttlh 10 - 30 75 - 30 150 average input capacitance, ci any input - 5 - - 5 - 506 +85 70 140 2500 0.25 05 -012 -025 units ns ns pf units p.a v v v ma p.a figa - tvplcal propagatlondelav time 1'5. load capacitance. :::. ~;.:~ :~~~o~~~~:: 1;:::- ::: : cd40)o.~i!~' 'oo~1ljjj ~ ii.;---.!o!! |
